Qore Programming Language  0.8.11.1
macros-ia64.h
1 /* -*- mode: c++; indent-tabs-mode: nil -*- */
2 /*
3  macros-itanium.h
4 
5  assembly macros for the Itanium (IA-64) architecture
6 
7  Qore Programming Language
8 
9  Copyright (C) 2003 - 2014 David Nichols
10 
11  Permission is hereby granted, free of charge, to any person obtaining a
12  copy of this software and associated documentation files (the "Software"),
13  to deal in the Software without restriction, including without limitation
14  the rights to use, copy, modify, merge, publish, distribute, sublicense,
15  and/or sell copies of the Software, and to permit persons to whom the
16  Software is furnished to do so, subject to the following conditions:
17 
18  The above copyright notice and this permission notice shall be included in
19  all copies or substantial portions of the Software.
20 
21  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
24  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
26  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
27  DEALINGS IN THE SOFTWARE.
28 
29  Note that the Qore library is released under a choice of three open-source
30  licenses: MIT (as above), LGPL 2+, or GPL 2+; see README-LICENSE for more
31  information.
32 */
33 
34 #ifndef _QORE_MACHINE_MACROS_H
35 #define _QORE_MACHINE_MACROS_H
36 
37 #define STACK_DIRECTION_DOWN 1
38 
39 #ifdef __GNUC__
40 #ifdef __LP64__
41 
42 #define HAVE_ATOMIC_MACROS
43 #define HAVE_CHECK_STACK_POS
44 
45 // 64-bit IA-64 atomic operations borrowed from linux
46 #define ia64_cmpxchg4_acq(ptr, new, old) ({ \
47  unsigned long ia64_intri_res; \
48  asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
49  asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \
50  "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
51  (int)ia64_intri_res; \
52 })
53 
54 static __inline__ int ia64_atomic_add (int i, volatile int *v) {
55  int old, vnew;
56 
57  do {
58  old = *v;
59  vnew = old + i;
60  } while (ia64_cmpxchg4_acq(v, vnew, old) != old);
61  return vnew;
62 }
63 
64 static __inline__ int ia64_atomic_sub (int i, volatile int *v) {
65  int old, vnew;
66 
67  do {
68  old = *v;
69  vnew = old - i;
70  } while (ia64_cmpxchg4_acq(v, vnew, old) != old);
71  return vnew;
72 }
73 
74 static inline void atomic_inc(volatile int *a) {
75  ia64_atomic_add(1, a);
76 }
77 
78 // returns 1 when counter reaches zero, 0 if not
79 static inline int atomic_dec(volatile int *a) {
80  return !ia64_atomic_sub(1, a);
81 }
82 
83 static inline size_t get_stack_pos() {
84  size_t addr;
85  asm volatile ("mov %0=sp" : "=r" (addr));
86  return addr;
87 }
88 
89 static inline size_t get_rse_bsp() {
90  size_t addr;
91  asm volatile ("mov %0=ar.bsp" : "=r" (addr));
92  return addr;
93 }
94 
95 #endif // #ifdef __LP64__
96 #endif // #ifdef __GNUC__
97 
98 #ifdef __HP_aCC
99 #ifdef __LP64__
100 
101 #define HAVE_ATOMIC_MACROS
102 #define HAVE_CHECK_STACK_POS
103 
104 // these routines are implemented in assembler
105 extern "C" void atomic_inc(int *v);
106 extern "C" int atomic_dec(int *v);
107 extern "C" size_t get_stack_pos();
108 extern "C" size_t get_rse_bsp(); // get ia64 Register Stack Engine backing store pointer
109 
110 #endif // #ifdef __LP64__
111 #endif // #ifdef __HP_aCC
112 
113 #endif // #ifndef _QORE_MACHINE_MACROS_H
114